When taken LOW, data at the parallel inputs is loaded directly into the register independent of the state of the clock. Parallel loading is inhibited as long as the SHIFT/LOAD input is HIGH. Data transfer occurs on the positive going edge of the clock. Holding either of the CLOCK inputs high inhibits clocking, and holding either CLOCK input low with the SHIFT/LOAD input high enables the other CLOCK input. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function. ![]() Parallel inputs to each stage are enabled by a low level at the SHIFT/LOAD input.Īlso included is a gated CLOCK input and a complementary output from the eighth bit. ![]() This 8-bit serial shift register shifts data from QA to QH when clocked. ![]() It has the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. The 74HC165 high speed PARALLEL-IN/SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-gate CMOS technology.
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